1. Field of the Invention
The present invention relates in general to electrically erasable programmable flash memories, and more particularly to a flash memory with a negative voltage generator for data erasure, which is capable of performing a data erase operation by regulating a gate voltage of a memory cell transistor according to the level of a supply voltage instead of controlling a source voltage of the cell transistor while consuming a large amount of current, so as to significantly improve its erase characteristic.
2. Description of the Prior Art
Generally, because nonvolatile memories have the advantage that data stored therein is subjected to no loss even though power is interrupted, they are widely used for the storage of data in a PC Bios, Set-top Box, printer, network server, etc. Recently, the nonvolatile memories have often been used even in fields such as a digital camera and cellular phone.
Among the nonvolatile memories, flash memories of an electrically erasable programmable read only memory (EEPROM) type have a function of erasing data in all memory cells in the lump. Such flash memories are classified into a NOR-type flash memory wherein at least two memory cell transistors are connected in parallel to one bit line and a NAND-type flash memory wherein at least two memory cell transistors are connected in series to one bit line.
FIG. 1 is a view illustrating the operation of a conventional flash memory with a negative voltage generator for data erasure. The flash memory is of the EEPROM type and the negative voltage generator is used for the erasure of data in memory cells in the flash memory and here denoted by the reference numeral 20. As shown in FIG. 1, the negative voltage generator 20 comprises a charge pump 22 for pumping a negative charge to supply a negative voltage to a control gate 14 of a memory cell transistor for the erasure of data in the associated cell, and a regulator 24 for regulating the level of an output voltage VEEI from the charge pump 22 according to the level of a supply voltage VCC.
In addition to the negative voltage generator 20, the flash memory further comprises a negative voltage supply 30 for supplying the voltage VEEI of the level regulated by the regulator 24 to the control gate 14 of the memory cell transistor for the erasure of data in the associated cell, and a Vs voltage generator 40 for regulating the level of the supply voltage VCC and applying the resultant voltage to a source 18 of the cell transistor.
The operation of the conventional flash memory with the above-mentioned construction will hereinafter be described briefly.
For a data erase operation, the negative voltage supply 30 supplies the output voltage from the negative voltage generator 20 to the control gate 14 of the cell transistor, and the Vs voltage generator 40 supplies its output voltage to the source 18 of the cell transistor. At this time, a drain 16 of the cell transistor floats (F). Also, electrons charged on a floating gate 12 of the cell transistor are emitted to the source 18 due to a Fowler-Nordheim tunneling effect based on a strong electric field formed between the floating gate 12 and the source 18.
However, in the above-mentioned conventional flash memory, because the voltage supplied to the source for the data erasure is generally obtained by a regulator, it is difficult to control the data erase operation based on the current supply capability, resulting in a degradation in the erase characteristic of the memory.